Newsgroups: sci.electronics
Subject: simple clock dbler: the solution!
From: elejw@ccu1.aukuni.ac.nz (James Williams)
Date: Wed, 14 Jul 1993 03:00:09 GMT

A week or 3 ago I posted a question about reccomendations for building a simple clock doubling circuit, to operate at approx 500kHz, using CMOS logic. +-------+ | hc86 | +-----------| | clkin ----+ | +--- clkout = 2*clkin +-N-R-+-N---+ | | | | C +-------+ | gnd where N is a NOT gate (hc04?) R is a 10k resistor C is a 47pf capacitor. The circuit functions quite well and is stable. If the Not gates are omitted, however, it becomes unstable, and gives variable width pulses. Thanks to everyone who made suggestions.